This invention relates to an ATM (Asynchronous Transfer Mode) communication network and, more particularly, to a segmentation and reassembly system incorporated in the ATM communication network.
Conventionally, the segmentation and reassembly system is operative on the ATM adaptation layer of the protocol for the broadband ISDN (Integrated Service Digital Network). The segmentation and reassembly system receives ATM cells, and extracts payloads from the ATM cells. The segmentation and reassembly system assembles the payloads into a frame, and supplies the frame to a data processing system for upper-level software through a bus system.
The segmentation and reassembly system accumulates the pieces of fixed-speed data such as voice data in a frame buffer. If the segmentation and reassembly system accumulates the pieces of voice data supplied through a single channel, the segmentation and reassembly system consumes a lot of time for completing the ATM cell. This results in undesirable time lag.
The segmentation and reassembly system accumulates the pieces of fixed-speed data such as voice data in a frame buffer. If the segmentation and reassembly system accumulates the pieces of voice data supplied through a single channel, the segmentation and reassembly system consumes long time for completing the ATM cell. This results in undesirable time lug.
Japanese Patent Publication of Unexamined Application No. 7-162437 discloses a solution. The prior art ATM cell builder disclosed in the Japanese Patent Publication of Unexamined Application includes a bus switch unit connected to a bus system and plural assembly units connected in parallel to the bus switch unit, and the bus system supplies pieces of voice data through plural channels or time slots to the bus switch unit. The bus switch unit assigns plural channels to each assembly unit, and distributes the pieces of voice data to the assembly units. The assembly unit forms a payload from the pieces of voice data information supplied through the plural channels, and an ATM header and a payload header are added to the payload. In this way, the prior art ATM cell builder assembles the ATM cell, and transfers it through the network.
When the ATM cell arrives at a ATM cell receiver, the payload is disassembled into the pieces of voice data, and pieces of voice data labeled with same discriminative symbol are assembled into a frame. Although the Japanese Patent Publication of Unexamined Application No. 7-162437 is silent as to the data transfer from the ATM receiver to a data processing system for upper-level software, the bus system would be used.
Thus, the prior art segmentation and reassembly system eliminates the time lag due to the assembly work from the data transfer. However, the prior art segmentation and reassembly system suffers from low throughput due to congestion on the bus system.
It is therefore an important object of the present invention to provide a segmentation and reassembly system, which achieves a high throughput.
It is also an important object of the present invention to provide a segmentation and reassembly system, which allows the manufacturer to reduce the production cost of an associated data processing system.
To accomplish the object, the present invention proposes to share load between at least one exclusive interface and a CPU (Central Processing Unit) interface.
In accordance with one aspect of the present invention, there is provided a segmentation and reassembly system cooperating with a data processing system having at least one central processing unit connected through a CPU interface and special purpose engines, and the segmentation and reassembly system comprises a plurality of frame buffers for storing pieces of data selectively supplied from first ATM cells and a processing means connected to the plurality of frame buffers for selectively accessing the pieces of data and selectively supplying at least selected pieces of data to the special purpose engines through an exclusive interface for modifying the pieces of data, if necessary.